hello world in bare-metal rust / risc-v.
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Updated
Aug 26, 2023 - Rust
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
hello world in bare-metal rust / risc-v.
RISCV decoder / encoder library written in Rust
This is a RISC-V process library
tiny secure bootloader for embedded device written in Rust
Device support crate for WCH's CH32V MCUs: CH32V003, CH32V103, CH32V203, CH32V208, CH32V307, ...
Write an mini RISC-V operating system with Rust, just for fun!