Implementing an Assembler & Processor using the RISC-V instruction set and arm.

fetch -> decode -> execute -> memory access -> write back

For testing the cpu, clone and build the riscv-tests. The tests can be found in the modules/ folder. Please follow along the installation guide.

Run the tests via:

python riscv_cpu.py

Verilog

./run_arm32_cpu.sh test/subtract.hex

Disclaimer: Unfinished

Run the Assembler via:

python riscv_asm.py testfs/riscv_minimal.s

Prequisits: Cross-Compiler (if you are not on a ARM architecture natively)

sudo apt install gcc gcc-arm-linux-gnueabi binutils-arm-linux-gnueabi gcc-aarch64-linux-gnu binutils-aarch64-linux-gnu make

python arm_asm.py testfs/subtract.s
# Run automatic tests with
python -m unittest

Run the bash script to investigate the desired output of the assembler.

./run_arm32_tests.sh

Source -> Preprocessor -> Compiler -> assembly (.asm) -> Assembler -> object (.o) -> (+ Libraries) Linker -> Executable

• ARM Docs A32
• ARM Instructions Layout

MNEMONIC{S}{condition} {Rd}, Operand1, Operand2

MNEMONIC     - Short name (mnemonic) of the instruction
{S}          - An optional suffix. If S is specified, the condition flags are updated on the result of the operation
{condition}  - Condition that is needed to be met in order for the instruction to be executed
{Rd}         - Register (destination) for storing the result of the instruction
Operand1     - First operand. Either a register or an immediate value 
Operand2     - Second (flexible) operand. Can be an immediate value (number) or a register with an optional shift

• Course: Computer Systems Organization
• Unofficial RISC-V Manual: Additional manuscript about RISC-V along the official RISC-V Manual.
• riscv-isadoc: Instruction Set docs on Github.
• riscv-dbg