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Would it be possible to communicate between 2 host via ethernet?
#86
by tangyuelm
was closed Apr 14, 2023
”ERROR: [v++ 60-398] cf2sw failed“ when run "p2p_bandwidth" with SmartSSD U.2
#85
by sdudyl
was closed Apr 14, 2023
utils.mk:30: *** XILINX_VITIS variable is not set, please set correctly and rerun. Stop.
#79
by bpradeep508
was closed Feb 15, 2023
utils.mk:30: *** XILINX_VITIS variable is not set, please set correctly and rerun. Stop.
#78
by bpradeep508
was closed Feb 15, 2023
utils.mk:30: *** XILINX_VITIS variable is not set, please set correctly and rerun. Stop.
#77
by bpradeep508
was closed Feb 15, 2023
Segmentation fault (core dumped) after programming .xclbin file to U50 board
#76
by IskandarZhang
was closed Sep 3, 2022
Resources exhausted for {HBM[0:4]} error in hbm_simple demo
#75
by IskandarZhang
was closed Sep 3, 2022
must be enabled with the -std=c++0x or -std=gnu++0x compiler options
#70
by crizy
was closed Aug 8, 2022
Is it possible to do software emulation without Xilinx FPGA and run the code on CPU?
#68
by enes1994
was closed Jul 15, 2022
[XRT] ERROR: See dmesg log for details. err = -22 in cpp_kernels/simple_vadd
#67
by xooxit
was closed Jun 23, 2022
common/includes/xcl2/xcl2.cpp:46 Error calling err = cl::Platform::get(&platforms), error code is: -1001
#62
by crizy
was closed Jul 12, 2022
providing --clock.defaultFreqHz on Alveo U200 2021.1 does not work / hangs
#58
by mayyxeng
was closed Apr 5, 2022
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Updated in the last three days: updated:>2024-06-09.