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Tremont (microarchitecture): Revision history


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  • curprev 09:4509:45, 2 February 2021115.134.189.39 talk 14,642 bytes +209 https://github.com/InstLatx64/InstLatx64/blob/master/GenuineIntel/GenuineIntel00906C0_JasperLake_CPUID01.txt L2 Unified Cache: 1536 KB, 12-way Associative, 64-byte Line L3 Unified Cache: 4 MB, 16-way Associative, 64-byte Line undo

12 January 2021

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